1002_DESIGN OF DIGITAL SYSTEMS
Course Period：From2012-02-20 ~ Any Time
Course Intro
Course Plan
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00_Digital System Design
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01_Binary Systems
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02_Boolean Algebra and Logic Gates
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03_Gate-Level Minimization
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04_Combinational Logic
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05_Synchronous Sequential Logic
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05_Synchronous Sequential Logic
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06_Registers and Counters
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07_Memory
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Digital System Design_grade
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Final_exam_99-2
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Future_study
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Grade-statistics
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Homework 1
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Homework 1_ans
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Homework 2
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Homework 2_ans
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Homework 3
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Homework 3_ans
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Homework 4
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Homework 4_ans
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Homework 5
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Homework 5_Answer
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Homework 6-1
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Homework 6-1_ans
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Homework 6-2
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Homework 6-2_ans
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Homework-QuartusII
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Introduction to SOC
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Midterm_exam_99-2
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QuartusII_tutorial
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QuartusII_tutorial_v2
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Sequential-ckt_quartus_example
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answer_finalexam_100-2
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answer_finalexam_99-2
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answer_midterm
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mid_ans_100-2
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上課參與
Co-Instructor(s)
謝東佑
謝東佑
Co-Instructor(s)
曾信遠
曾信遠
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