1031_HARDWARE DESCRIPTION LANGUAGES
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
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00_outline (2014f)
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01_Verilog structural and dataflow modeling (2014f)
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02_Verilog behavioral level modeling (2014f)
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03_Verilog useful modeling (2014f)
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04_Verilog 1995 vs 2001 (2014f)
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05_Verilog synthesis and design flows (2014f)
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06_Verilog Codes for Basic Components (2014f)
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07_VHDL data type
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08_VHDL concurrent and sequential
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09_VHDL component and package
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10_VHDL review
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11_Verilog versus VHDL
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12_RTL Coding Rules
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DC&Xilinx_demo
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HW1_8-bit adder in three Verilog levels (2014f)
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HW2_32-bit pipelined ALU (2014f)
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HW3
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HW4_color conversion and edge detection on ASIC (2014f)
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HW5 (bonus)
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IEEE std 1076 (VHDL reference manual)
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IEEE std 1364-2005 (Verilog HDL)
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ModelSim_Demo
Co-Instructor(s)
蕭勝夫
蕭勝夫
Co-Instructor(s)
王靖惠
王靖惠
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