1041_HARDWARE DESCRIPTION LANGUAGES
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
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00_outline (2015f)
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01_Verilog structural and dataflow modeling (2015f)
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02_Verilog behavioral level modeling (2015f)
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03_logic synthesis and design flow (2015f)
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04_Verilog useful modeling (2015f)
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05_Verilog 1995 vs 2001 (2015f)
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06_Coding for logic synthesis (2015f)
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07_Verilog Codes for Basic Components (2015f)
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08 Verilog Codes for Advanced Components (2015f)
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09_VHDL data type
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10_VHDL concurrent and sequential
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11_VHDL component and package
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12_VHDL review
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13_Verilog versus VHDL
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14_RTL Coding Rules
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HW 3_color conversion and edge detection on RISC (2015f)
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HW1_8-bit adder in three Verilog levels (2015f)
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HW2_32-bit pipelined ALU (2015f)
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HW3
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IEEE std 1076 (VHDL reference manual)
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IEEE std 1364-2001 (Verilog HDL)
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THUMB RISC codes (VHDL)
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THUMB RISC codes (Verilog)
Co-Instructor(s)
蕭勝夫
蕭勝夫
Co-Instructor(s)
李尚諭
李尚諭
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