1051_HARDWARE DESCRIPTION LANGUAGES
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
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00_outline and overivew (2016f)
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01_Verilog structural and dataflow modeling (2016f)
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02_Verilog behavioral level modeling (2016f)
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03_logic synthesis and design flow (2016f)
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04_pipelined THUMB CPU
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05_Verilog Codes for Basic Components (2016f)
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06_Verilog useful modeling (2016f)
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07_Verilog 1995 vs 2001 (2016f)
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08_Coding for logic synthesis (2016f)
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09_Verilog Codes for Advanced Components (2016f)
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10_VHDL data type
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11_VHDL concurrent and sequential
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12_VHDL component and package
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13_VHDL review
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14_RTL Coding Rules
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15_Verilog versus VHDL
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HW1_modeling an adder in three Verilog levels (2016f)
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HW2_pipelined multiply-add in both RTL and gate-level (2016f)
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HW3_pipelined THUMB CPU
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HW4_pipelined MIPS CPU
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HW5_color conversion and Sorbel edge operation
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IEEE std 1076 (VHDL reference manual)
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IEEE std 1364-2005 (Verilog HDL)
Co-Instructor(s)
蕭勝夫
蕭勝夫
Co-Instructor(s)
蔡正言
蔡正言
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