1052_實用數位系統設計
上課期間：從 2017-02-21 到 無限期
課程介紹
課程安排
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00_Overview
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01_Introduction
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02-II_Basic Verilog Coding &Combinational Logic
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02-I_Basic Verilog Coding &Combinational Logic
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03-II_Workstation-operation-flow
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03-I_Introduction to Workstation Environment
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04_Adder designs
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05_Synopsys Design Compiler Logic Synthesis EDA Tool
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06_Basic Verilog Coding &Sequential Logic
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07_Multiplier designs_partI
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08_RTL Coding Guildlines
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09_Verification
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Comparison of Various Multipliers
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Covered – Verilog Code Coverage Analyzer
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HW-Note
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HW1-1
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HW1成績
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Homework 3
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Homework4
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Homework_Bonus
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Midterm Examination_實用數位系統設計
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Notepad++ opration step
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PDSD105_Midterm_修正
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PDSD_HW2_Score
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PDSD_HW2_Solution
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PSPAD&NotePad++
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Project
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Test cases
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covered-0.7.10.tar
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covered_example
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simvision
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workstation
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貢獻確認
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期中考詳解
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期末專題分組名單
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期末專題分組名單_更正
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期末報告封面與貢獻確認
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實用數位作業總成績
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實用數位期中考成績 (1)
教師 / 謝東佑
教師 / 林銘軍
教師 / 陳昭如
教師 / 何季軒
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