1071_HARDWARE DESCRIPTION LANGUAGES
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
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00_outline and overivew (2018f)
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01_Verilog structural and dataflow modeling (2018f)
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02_Verilog behavioral level modeling (2018f)
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03_logic synthesis and design flow (2018f)
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04_pipelined THUMB CPU (2018f)
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05_Verilog Codes for Basic Components (2018f)
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06_Verilog useful modeling (2018f)
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07_Verilog 1995 vs 2001 (2018f)
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08_Coding for logic synthesis (2018f)
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09_2 Verilog review
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09_2_More on Synchronizer (2018f)
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09_Verilog Codes for Advanced Components (2018f)
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10_VHDL data type (2018f)
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11_VHDL concurrent and sequential (2018f)
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12_VHDL component and package (2018f)
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13_VHDL review (2018f)
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14_Verilog versus VHDL (2018f)
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15_RTL Coding Rules, including Verification (2018f)
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16_1 SystemVerilog vs Verilog (2018f)
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HW1_modeling an adder in three Verilog levels (2018f)
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HW2_pipelined multiply-add in both RTL and gate-level (2018f)
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HW3_32-bit pipelined ALU (2018f)
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HW4_pipelined THUMB CPU
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HW5_pipelined MIPS CPU
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HW6_color conversion and Sorbel edge operation using MIPS (2018f)
Co-Instructor(s)
蕭勝夫
蕭勝夫
Co-Instructor(s)
陳俊良
陳俊良
Co-Instructor(s)
張烜睿
張烜睿
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