1072_PRACTICAL DIGITAL SYSTEMS DESIGN
Registration：FromNow ~ Any Time
Course Period：From2019-02-19 ~ Any Time
Course Intro
Course Plan
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00_Overview
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01_Introduction
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02-II_Basic Verilog Coding &Combinational Logic
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02-I_Basic Verilog Coding &Combinational Logic
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03-II_Workstation-operation-flow
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03-I_Introduction to Workstation Environment
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04_Adder designs
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05_Synopsys Design Compiler Logic Synthesis EDA Tool
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06_Basic Verilog Coding &Sequential Logic
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07_Multiplier designs
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08_RTL Coding Guildlines
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09_Verification
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107PDSD期末專題說明
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20170426_Midterm Examination
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Covered – Verilog Code Coverage Analyzer
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Covered
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HOWEWORK書面報告範例
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HW-Note
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HW1-1
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HW1-1成績(更新)
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HW1-2
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HW1-2成績(更新)
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HW2
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HW2_成績
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HW2_參考答案
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HW3
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HW3_成績
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HW4
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HW4成績
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Memory
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PDSD_final_project_tb_v4
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PDSD_期末成績(更新)
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Project
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SUMA180_256X5
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test_data
Co-Instructor(s)
謝東佑
謝東佑
Co-Instructor(s)
郭華鈞
郭華鈞
Co-Instructor(s)
卜仁
卜仁
Co-Instructor(s)
許家騰
許家騰
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