1081_硬體描述語言
上課期間：從 即日起 到 無限期
課程介紹
課程安排
-
00_outline and overivew (2019f)
-
01_Verilog structural and dataflow modeling (2019f)
-
02_Verilog behavioral level modeling (2019f)
-
03_logic synthesis and design flow (2019f)
-
04_Verilog Codes for Basic Components (2019f)
-
05_Verilog useful modeling (2019f)
-
06_Verilog 1995 vs 2001 (2019f)
-
07_Coding for logic synthesis (2019f)
-
08_Verilog Codes for Advanced Components (2019f)
-
09_02 THUMB instruction set
-
09_pipelined THUMB CPU (2019f)
-
10_Verilog review (2019f)
-
11_VHDL data type (2019f)
-
12_VHDL concurrent and sequential (2019f)
-
13_VHDL component and package (2019f)
-
14_VHDL review (2019f)
-
15_Verilog versus VHDL (2019f)
-
16_RTL Coding Rules, including Verification (2019f)
-
17_SystemVerilog vs Verilog (2019)
-
Appendix A (THUMB)
-
Gxsobel_cat
-
Gysobel_cat
-
HW1_modeling an adder in three Verilog levels (2019f)
-
HW2_pipelined multiply-add in both RTL and gate-level (2019f)
-
HW3_color conversion and Sorbel edge operation with line buffer (2019f)
-
HW4_32-bit pipelined ALU (2019f)
-
HW5_Sorbel operation using pipelined THUMB CPU (2019f)
-
Homework3說明
-
cat
-
thumb
-
thumb_defs
-
thumb_syn
教師 / 蕭勝夫
教師 / 吳翌星
教師 / 林鑫辰
相關課程
|
|
||||||
|
|
|
||||||
|
|
|
||||||
|