1081_HARDWARE DESCRIPTION LANGUAGES
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
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00_outline and overivew (2019f)
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01_Verilog structural and dataflow modeling (2019f)
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02_Verilog behavioral level modeling (2019f)
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03_logic synthesis and design flow (2019f)
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04_Verilog Codes for Basic Components (2019f)
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05_Verilog useful modeling (2019f)
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06_Verilog 1995 vs 2001 (2019f)
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07_Coding for logic synthesis (2019f)
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08_Verilog Codes for Advanced Components (2019f)
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09_02 THUMB instruction set
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09_pipelined THUMB CPU (2019f)
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10_Verilog review (2019f)
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11_VHDL data type (2019f)
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12_VHDL concurrent and sequential (2019f)
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13_VHDL component and package (2019f)
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14_VHDL review (2019f)
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15_Verilog versus VHDL (2019f)
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16_RTL Coding Rules, including Verification (2019f)
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17_SystemVerilog vs Verilog (2019)
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Appendix A (THUMB)
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Gxsobel_cat
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Gysobel_cat
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HW1_modeling an adder in three Verilog levels (2019f)
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HW2_pipelined multiply-add in both RTL and gate-level (2019f)
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HW3_color conversion and Sorbel edge operation with line buffer (2019f)
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HW4_32-bit pipelined ALU (2019f)
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HW5_Sorbel operation using pipelined THUMB CPU (2019f)
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Homework3說明
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cat
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thumb
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thumb_defs
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thumb_syn
Co-Instructor(s)
蕭勝夫
蕭勝夫
Co-Instructor(s)
吳翌星
吳翌星
Co-Instructor(s)
林鑫辰
林鑫辰
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