1082_PRACTICAL DIGITAL SYSTEMS DESIGN
Registration：FromNow ~ Any Time
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
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00_Overview
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01_Introduction
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02-I_Basic Verilog Coding &Combinational Logic
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02-II_Basic Verilog Coding &Combinational Logic
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03-I_Introduction to Workstation Environment
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03-II_Workstation-operation-flow
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04_Adder designs
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05_Synopsys Design Compiler Logic Synthesis EDA Tool
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06_Basic Verilog Coding &Sequential Logic
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07_Multiplier designs
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08_RTL Coding Guildlines
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09_Verification
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Covered
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Spyglass操作手冊
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DesignWare操作手冊
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20170426_Midterm Examination
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教室分配
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HW-Note
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HW1-1
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HW1-2
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HW3
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HW4
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HOWEWORK書面報告範例
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HW1常見錯誤
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HW1-1 成績
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HW1-2成績
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HW3成績
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HW4成績
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Memory-usage
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Memory usage_example
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Project
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project說明
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project_example_version1
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midterm_ref_ans
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midterm_Q5Q8_ref_ans
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project_training
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Project-files
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分組名單
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簡報示例
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專題額外加分說明
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PDSD_TA project report
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期末專題注意事項
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performance表格
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期末專題成績
Co-Instructor(s)
謝東佑
謝東佑
Co-Instructor(s)
吳閏琮
吳閏琮
Co-Instructor(s)
蔡京燁
蔡京燁
Co-Instructor(s)
莊學叡
莊學叡
Co-Instructor(s)
陳則佑
陳則佑
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