1091_HARDWARE DESCRIPTION LANGUAGES
Registration：FromNow ~ Any Time
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
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00_outline and overivew (2020f)
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01_Verilog structural and dataflow modeling (2020f)
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02_Verilog behavioral level modeling (2020f)
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03_logic synthesis and design flow (2020f)
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04_Verilog Codes for Basic Components (2020f)
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05_pipelined THUMB CPU (2020f)
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06_Verilog useful modeling (2020f)
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07_Verilog 1995 vs 2001 (2019f)
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08_Coding for logic synthesis (2020f)
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09_Verilog Codes for Advanced Components (2020f)
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10_Verilog review (2020f)
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VHDL_1_data type (2020f)
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VHDL_2_concurrent and sequential (2020f)
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VHDL_3_ component and package (2020f)
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13_VHDL_4_review (2020f)
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14_RTL Coding Rules, including Verification (2020f)
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15_SystemVerilog vs Verilog (2020f)
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IEEE std 1364-2001 (Verilog HDL)
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HDL_midterm exam_2020f (with answers)
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HW1_modeling an adder in three Verilog levels (2020f)
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HW2_pipelined multiply-add in both RTL and gate-level (2020f)_v5
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HW3_Design Compiler Optimization Commands for pipelined THUMB CPU (2020f)_revised
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HW4_color conversion and Sorbel edge operation with line buffer (2020f)
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HW5_The first two Conv layers in VGG-16.
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HW6_Design Compiler Optimization Commands for pipelined THUMB CPU_VHDL (2020f)_revised
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HW3_Appendix A (THUMB)
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modelsim教學_v4
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Xilinx_Vivado_v3
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Design Compiler_v1
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HW3所需檔案
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Conv._Line Buffer_Padding_Tutorial
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HW4_Requirement
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HDL_HW6_Requirement
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HDL_HW5_所需檔案
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16_Verilog versus VHDL (2020f)
Co-Instructor(s)
蕭勝夫
蕭勝夫
Co-Instructor(s)
李宏慶
李宏慶
Co-Instructor(s)
蔡柏慶
蔡柏慶
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