1091_HARDWARE DESCRIPTION LANGUAGES
Registration：FromNow ~ Any Time
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
-
00_outline and overivew (2020f)
-
01_Verilog structural and dataflow modeling (2020f)
-
02_Verilog behavioral level modeling (2020f)
-
03_logic synthesis and design flow (2020f)
-
04_Verilog Codes for Basic Components (2020f)
-
05_pipelined THUMB CPU (2020f)
-
06_Verilog useful modeling (2020f)
-
07_Verilog 1995 vs 2001 (2019f)
-
08_Coding for logic synthesis (2020f)
-
09_Verilog Codes for Advanced Components (2020f)
-
10_Verilog review (2020f)
-
VHDL_1_data type (2020f)
-
VHDL_2_concurrent and sequential (2020f)
-
VHDL_3_ component and package (2020f)
-
13_VHDL_4_review (2020f)
-
14_RTL Coding Rules, including Verification (2020f)
-
15_SystemVerilog vs Verilog (2020f)
-
IEEE std 1364-2001 (Verilog HDL)
-
HDL_midterm exam_2020f (with answers)
-
HW1_modeling an adder in three Verilog levels (2020f)
-
HW2_pipelined multiply-add in both RTL and gate-level (2020f)_v5
-
HW3_Design Compiler Optimization Commands for pipelined THUMB CPU (2020f)_revised
-
HW4_color conversion and Sorbel edge operation with line buffer (2020f)
-
HW5_The first two Conv layers in VGG-16.
-
HW6_Design Compiler Optimization Commands for pipelined THUMB CPU_VHDL (2020f)_revised
-
HW3_Appendix A (THUMB)
-
modelsim教學_v4
-
Design Compiler_v1
-
Xilinx_Vivado_v3
-
HW3所需檔案
-
Conv._Line Buffer_Padding_Tutorial
-
HW4_Requirement
-
HDL_HW6_Requirement
-
HDL_HW5_所需檔案
-
16_Verilog versus VHDL (2020f)
Co-Instructor(s)
蕭勝夫
蕭勝夫
Co-Instructor(s)
蔡柏慶
蔡柏慶
Co-Instructor(s)
李宏慶
李宏慶
Related Courses
|
|
||||||
|
|
|
||||||
|
|
|
||||||
|