1101_HARDWARE DESCRIPTION LANGUAGES
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
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00_outline and overivew (2021f)
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hdl_00 (video)
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02_Verilog behavioral level modeling (2021f)
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HW1_modeling an adder in three Verilog levels (2021f)
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01_Verilog structural and dataflow modeling (2021f)
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03_logic synthesis and design flow (2021f)
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HW2_pipelined multiply-add in both RTL and gate-level (2021f)_v5
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HW3_所需附件與程式碼
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HW4_color conversion and Sorbel edge operation with line buffer (2021f)
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07_Verilog 1995 vs 2001 (2021f)
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05_pipelined THUMB CPU (2021f)
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04_Verilog Codes for Basic Components (2021f)
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06_other modeling techniques (2021f)
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04_basic components (video)
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05_thumb cpu (video)
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06_other techniques (video)
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07_verilog 1995 vs 2001 (video)
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09 (2021f)_VHDL_1_data type
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10 (2021f)_VHDL_2_concurrent and sequential
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11 (2021f)_VHDL_3_component, package, and configuration
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08 (2021f)_Verilog Codes for Advanced Components
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12_Verilog versus VHDL (2021f)
Co-Instructor(s)
蕭勝夫
蕭勝夫
Co-Instructor(s)
曾歆庭
曾歆庭
Co-Instructor(s)
郭家豪
郭家豪
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