1112_PRACTICAL DIGITAL SYSTEMS DESIGN_EE3705
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
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00_Overview
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2020_grad_cell
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01_Introduction
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02-I_Basic Verilog Coding &Combinational Logic
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02-II_Basic Verilog Coding &Combinational Logic
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03_SOC Server Overview
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03-2_Operation in Workstation
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04_Adder designs
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05_Synopsys Design Compiler Logic Synthesis EDA Tool
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06_Basic Verilog Coding &Sequential Logic
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07_Multiplier designs
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08_RTL Coding Guildlines
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09_Verification
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PDSD作業注意事項
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20170426_Midterm Examination
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HW1-1
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HW1-2
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HW2
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HW3
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String Matching Engine
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期末專題說明_TA_2023
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DesignWare操作手冊
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Coverage
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期末專題分數
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期中構想分數
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期中進度分數
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期中考分數
Co-Instructor(s)
謝東佑
謝東佑
Co-Instructor(s)
郭瀚睿
郭瀚睿
Co-Instructor(s)
張瑋之
張瑋之
Co-Instructor(s)
林佩璇
林佩璇
Co-Instructor(s)
何柏震
何柏震
Co-Instructor(s)
鄞振祐
鄞振祐
Co-Instructor(s)
王翊瑄
王翊瑄
Co-Instructor(s)
陳宗群
陳宗群
Co-Instructor(s)
甄致瑜
甄致瑜
Co-Instructor(s)
鄭育玟
鄭育玟
Co-Instructor(s)
徐敬昕
徐敬昕
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