1002_SYSTEM-ON-CHIP DESIGN
Registration：FromNow ~ Any Time
Course Period：From2012-02-20 ~ Any Time
Course Intro
Course Plan
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00_System-on-chip Design
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01_Introduction
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02_Basic Verilog Coding &Combinational Logic
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03_Basic Verilog Coding &Sequential Logic
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04_CPU Design Basics
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05_Pipelined CPU Design
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06_RTL Coding Guildlines
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Cell-Based Physical Design Flow Using Design Vision and SOC Encounter EDA Tools
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FunctionallVerification_TransEDA
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HW-Note
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Homework1-1
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Homework1-2
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Homework2
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Homework3
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Homework4
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Homework5
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Introduction to Workstation Environment
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Midterm Examination_99-2
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Project
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SOC分組名單
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Synopsys Design Compiler Logic Synthesis EDA Tool
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grade
Co-Instructor(s)
謝東佑
謝東佑
Co-Instructor(s)
謝依潔
謝依潔
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