1012_SYSTEM-ON-CHIP DESIGN
Registration：FromNow ~ Any Time
Course Period：From2013-02-24 ~ Any Time
Course Intro
Course Plan
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00_System-on-chip Design
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01_Introduction
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02-II_Basic verilog coding for combinational building blocks
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02-I_Basic verilog coding for combinational building blocks
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03_Basic Verilog Coding for Sequential Logic
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04_CPU Design Basics
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05_Pipelined CPU Design
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06_ARM Processor Basics-partII
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06_ARM Processor Basics
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07_RTL Coding Guildlines
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08_Verification
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09_Design for testability (DFT) and reliability
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Design rule check nLint
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FunctionallVerification_TransEDA
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HW-Note
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HW1-1
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HW1-2
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HW1-2_Grade
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HW1_Grade
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HW2_Grade
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HW3
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HW3_Grade
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HW4
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HW4_Grade
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HW5
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HW5_Grade
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Memory Complier
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Midterm Examination_100-2
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Midterm Examination_99-2
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Synopsys Design Compiler Logic Synthesis EDA Tool
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Workstation-operation-flow
Co-Instructor(s)
謝東佑
謝東佑
Co-Instructor(s)
紀雅修
紀雅修
Co-Instructor(s)
楊 碩
楊 碩
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