1021_PRACTICAL DIGITAL SYSTEMS DESIGN
Registration：FromNow ~ Any Time
Course Period：From2013-09-23 ~ Any Time
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Course Intro

Course Plan

  • 00_Overview
  • 01_Introduction
  • 02-II_Basic Verilog Coding &Combinational Logic
  • 02-I_Basic Verilog Coding &Combinational Logic
  • 03_Basic Verilog Coding &Sequential Logic
  • 04_Bus and a simple processor design
  • 05_RTL Coding Guildlines
  • 06_Arithmetic and Logic Circuit Design
  • 07_Memory systems
  • 08_Cache Memory Design
  • Calibre_verification
  • Exercise
  • HW-Note
  • HW1-1
  • HW1-2
  • HW1_1_Score
  • HW1_2_Score
  • HW2
  • HW2_Score
  • HW3
  • HW3_Score
  • HW4
  • HW4_Score
  • Introduction to Workstation Environment
  • Memory Compiler Training
  • Memory Complier
  • Midterm Examination_101-1
  • Midterm_1_Score
  • Midterm_2_Score
  • Project
  • Project_Score
  • SOC_Encounter
  • Synopsys Design Compiler Logic Synthesis EDA Tool
  • Workstation-operation-flow
  • 分組名單
Co-Instructor(s)
謝東佑
Co-Instructor(s)
王致皓
Co-Instructor(s)
池宗亮

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LINE sharing feature only supports mobile devices