1031_系統晶片設計
上課期間：從 2014-09-17 到 無限期
課程介紹
課程安排
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00_System-on-chip Design
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01-II_Basic verilog coding for combinational building blocks
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01-I_Basic verilog coding for combinational building blocks
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02_Basic Verilog Coding for Sequential Logic
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03_CPU Design Basics
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04_Pipelined CPU Design
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05_Cache Memory Design
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06_Branch Prediction
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07_ARM Processor Basics
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08_RTL Coding Guildlines
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09_Verification
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Covered – Verilog Code Coverage Analyzer
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Design Compiler
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Encounter_U18
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Encounter_example
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HW-Note
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HW1-1
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HW1-2
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HW2
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HW3
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HW4
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HW5
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IoT and Wearable design technology
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Memory Simulation and Synthesis
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Midterm Examination_ref
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Project
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Score_HW1_1
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Score_HW1_2
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Score_HW2
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Score_HW3
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Score_HW4
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Score_HW5
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Workstation-operation-flow
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afterenc_umc18
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covered-0.7.10.tar
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covered_example
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synthesis_and_memory
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參考資料_HOWEWORK1書面報告
教師 / 謝東佑
教師 / 彭依涵
教師 / 王致皓
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