1041_系統晶片設計
上課期間：從 2015-09-16 到 無限期
課程介紹
課程安排
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00_System-on-chip Design
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01-II_Basic verilog coding for combinational building blocks
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01-I_Basic verilog coding for combinational building blocks
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02_Basic Verilog Coding for Sequential Logic
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03_CPU Design Basics
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04_Pipelined CPU Design
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05_Cache Memory Design
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06_Verification
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07_RTL Coding Guildlines
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08_Design for testability (DFT) and reliability
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Covered – Verilog Code Coverage Analyzer
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DRC_LVS
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Design Compiler
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HW-Note104
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HW1-1
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HW1-1_score
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HW1-2
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HW1-2_Score
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HW2
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HW2_Score
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HW3
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HW3_Score
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HW4
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HW4_Score
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HW5
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HW5_Score
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Introduction to Workstation Environment
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Layout_Encounter_U18
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Memory Simulation and Synthesis
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Memory_Datasheet_1024_32
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Midterm Examination_103-1
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Midterm Examination_99-2
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SOC_Design_Project_Score
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UMC_example
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Workstation-operation-flow
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covered-0.7.10.tar
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covered_example
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synthesis_and_memory
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參考資料_HOWEWORK1書面報告
教師 / 謝東佑
教師 / 鄭冠之
教師 / 王致皓
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