1041_SYSTEM-ON-CHIP DESIGN
Course Period：From2015-09-16 ~ Any Time
Course Intro
Course Plan
-
00_System-on-chip Design
-
01-II_Basic verilog coding for combinational building blocks
-
01-I_Basic verilog coding for combinational building blocks
-
02_Basic Verilog Coding for Sequential Logic
-
03_CPU Design Basics
-
04_Pipelined CPU Design
-
05_Cache Memory Design
-
06_Verification
-
07_RTL Coding Guildlines
-
08_Design for testability (DFT) and reliability
-
Covered – Verilog Code Coverage Analyzer
-
DRC_LVS
-
Design Compiler
-
HW-Note104
-
HW1-1
-
HW1-1_score
-
HW1-2
-
HW1-2_Score
-
HW2
-
HW2_Score
-
HW3
-
HW3_Score
-
HW4
-
HW4_Score
-
HW5
-
HW5_Score
-
Introduction to Workstation Environment
-
Layout_Encounter_U18
-
Memory Simulation and Synthesis
-
Memory_Datasheet_1024_32
-
Midterm Examination_103-1
-
Midterm Examination_99-2
-
SOC_Design_Project_Score
-
UMC_example
-
Workstation-operation-flow
-
covered-0.7.10.tar
-
covered_example
-
synthesis_and_memory
-
參考資料_HOWEWORK1書面報告
Co-Instructor(s)
謝東佑
謝東佑
Co-Instructor(s)
鄭冠之
鄭冠之
Co-Instructor(s)
王致皓
王致皓
Related Courses
|
|
||||||
|
|
|
||||||
|
|
|
||||||
|
|
|
||||||
|