1042_實用數位系統設計
報名期間：從 即日起 到 無限期
上課期間：從 2016-02-23 到 無限期
課程介紹
課程安排
-
.synopsys_dc
-
00_Overview
-
01_Introduction
-
02-II_Basic Verilog Coding &Combinational Logic
-
02-I_Basic Verilog Coding &Combinational Logic
-
03_Basic Verilog Coding &Sequential Logic
-
04_Memory usage
-
05_RTL Coding Guildlines
-
06_Adder designs
-
07_Multiplier designs
-
Exp1
-
HW-Note
-
HW1_score
-
HW2
-
HW2_score
-
HW3
-
HW3_score
-
Layout_Encounter_U18
-
Memory usage examples
-
Project
-
Socre
-
Synopsys Design Compiler Logic Synthesis EDA Tool
-
UMC_example
-
Workstation-operation-flow
-
afterenc_umc18
-
nLint_file
教師 / 謝東佑
教師 / 鐘振嘉
教師 / 吳美蓉
相關課程
|
|
||||||
|
|
|
||||||
|
|
|
||||||
|
|
|
||||||
|