1042_PRACTICAL DIGITAL SYSTEMS DESIGN
Registration：FromNow ~ Any Time
Course Period：From2016-02-23 ~ Any Time
Course Intro
Course Plan
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.synopsys_dc
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00_Overview
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01_Introduction
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02-II_Basic Verilog Coding &Combinational Logic
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02-I_Basic Verilog Coding &Combinational Logic
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03_Basic Verilog Coding &Sequential Logic
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04_Memory usage
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05_RTL Coding Guildlines
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06_Adder designs
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07_Multiplier designs
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Exp1
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HW-Note
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HW1_score
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HW2
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HW2_score
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HW3
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HW3_score
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Layout_Encounter_U18
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Memory usage examples
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Project
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Socre
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Synopsys Design Compiler Logic Synthesis EDA Tool
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UMC_example
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Workstation-operation-flow
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afterenc_umc18
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nLint_file
Co-Instructor(s)
謝東佑
謝東佑
Co-Instructor(s)
鐘振嘉
鐘振嘉
Co-Instructor(s)
吳美蓉
吳美蓉
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