1062_PRACTICAL DIGITAL SYSTEMS DESIGN
Course Period：From2018-03-06 ~ Any Time
LINE sharing feature only supports mobile devices

Course Intro

Course Plan

  • 00_Overview
  • 01_Introduction
  • 02-II_Basic Verilog Coding &Combinational Logic
  • 02-I_Basic Verilog Coding &Combinational Logic
  • 03-II_Workstation-operation-flow
  • 03-I_Introduction to Workstation Environment
  • 04_Adder designs
  • 05_Synopsys Design Compiler Logic Synthesis EDA Tool
  • 06_Basic Verilog Coding &Sequential Logic
  • 07_Multiplier designs
  • 08_RTL Coding Guildlines
  • 09_Verification
  • Coding-style-evaluation
  • Covered – Verilog Code Coverage Analyzer
  • Covered_example
  • HW-Note
  • HW1-1
  • HW1_參考解答
  • HW2_參考解答
  • HW2成績
  • HW3_參考解答
  • HW3成績
  • Homework1-2
  • Homework3
  • Homework_Bonus
  • Midterm Examination_實用數位系統設計
  • PDSD-工作站帳號
  • PDSD_mid
  • PDSD工作站連線
  • PDSD成績總表
  • PSPAD&NotePad++
  • Project
  • Test cases
  • covered-0.7.10.tar
  • nLint_example
  • simvision
  • synopsys_dc
  • workstation
  • 指令
  • 組別
  • 報告成績
  • 期末成績
  • 期末報告封面與貢獻確認
Co-Instructor(s)
謝東佑
Co-Instructor(s)
李寶茜
Co-Instructor(s)
邱育仁
Co-Instructor(s)
沈鑫泳
Co-Instructor(s)
吳品萱

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