1102_PRACTICAL DIGITAL SYSTEMS DESIGN_EE3705
Registration：FromNow ~ Any Time
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
-
110_PDSD_期末成績_V4
-
00_Overview
-
01_Introduction
-
02-I_Basic Verilog Coding &Combinational Logic
-
02-II_Basic Verilog Coding &Combinational Logic
-
03_SOC Server Overview
-
03-2_Operation in Workstation
-
04_Adder designs
-
05_Synopsys Design Compiler Logic Synthesis EDA Tool
-
06_Basic Verilog Coding &Sequential Logic
-
07_Multiplier designs
-
08_RTL Coding Guildlines
-
09_Verification
-
Final Project - Geofence
-
EX1
-
EX2
-
PDSD作業注意事項
-
HW1-1
-
HW1-2
-
HW2
-
HW3
-
20170426_Midterm Examination
-
Covered
-
PDSD_線上課程證書紀錄
Co-Instructor(s)
謝東佑
謝東佑
Co-Instructor(s)
陳維鴻
陳維鴻
Co-Instructor(s)
郭瀚睿
郭瀚睿
Co-Instructor(s)
何柏震
何柏震
Co-Instructor(s)
林敬偉
林敬偉
Related Courses
|
|
||||||
|
|
|
||||||
|
|
|
||||||
|
|
|
||||||
|