1121_系統晶片測試_EE5729
報名期間：從 即日起 到 無限期
上課期間：從 即日起 到 無限期
課程介紹
課程安排
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00_Overview
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01_Introduction
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02_Fault model
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03_Faul simulation
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04_Test generation
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05_Testability Analysis
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06_Design for testability
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07_BIST
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Midterm Examination_ref
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112SOCT_Midterm_Answer
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Homework Rule
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Homework1
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Homework2
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Homework3
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Homework4
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Homework5
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D-Algorithm Exercise
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Final Examination_ref
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HW Submission
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07_Logic BIST_Intro1
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08_Memory Testing_Intro
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112SOCT_Final_Answer
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00_Overview
-
01_Introduction
-
02_Fault model
-
03_Faul simulation
-
04_Test generation
-
05_Testability Analysis
-
06_Design for testability
-
07_BIST
-
Midterm Examination_ref
-
112SOCT_Midterm_Answer
-
Homework Rule
-
Homework1
-
Homework2
-
Homework3
-
Homework4
-
Homework5
-
D-Algorithm Exercise
-
Final Examination_ref
-
HW Submission
-
07_Logic BIST_Intro1
-
08_Memory Testing_Intro
-
112SOCT_Final_Answer
教師 / 謝東佑
教師 / 王翊瑄
教師 / 黃柏愷
教師 / 張瑋之
教師 / 林佩璇
教師 / 甄致瑜
教師 / 廖國宏
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