1121_SYSTEM-ON-CHIP TESTING_EE5729
Registration：FromNow ~ Any Time
Course Period：FromNow ~ Any Time
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Course Intro

Course Plan

  • 00_Overview
  • 01_Introduction
  • 02_Fault model
  • 03_Faul simulation
  • 04_Test generation
  • 05_Testability Analysis
  • 06_Design for testability
  • 07_BIST
  • Midterm Examination_ref
  • 112SOCT_Midterm_Answer
  • Homework Rule
  • Homework1
  • Homework2
  • Homework3
  • Homework4
  • Homework5
  • D-Algorithm Exercise
  • Final Examination_ref
  • HW Submission
  • 07_Logic BIST_Intro1
  • 08_Memory Testing_Intro
  • final exam
  • 00_Overview
  • 01_Introduction
  • 02_Fault model
  • 03_Faul simulation
  • 04_Test generation
  • 05_Testability Analysis
  • 06_Design for testability
  • 07_BIST
  • Midterm Examination_ref
  • 112SOCT_Midterm_Answer
  • Homework Rule
  • Homework1
  • Homework2
  • Homework3
  • Homework4
  • Homework5
  • D-Algorithm Exercise
  • Final Examination_ref
  • HW Submission
  • 07_Logic BIST_Intro1
  • 08_Memory Testing_Intro
  • final exam
Co-Instructor(s)
謝東佑
Co-Instructor(s)
王翊瑄
Co-Instructor(s)
黃柏愷
Co-Instructor(s)
張瑋之
Co-Instructor(s)
林佩璇
Co-Instructor(s)
甄致瑜
Co-Instructor(s)
廖國宏

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