1121_HARDWARE DESCRIPTION LANGUAGES_CSE668
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
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00_outline and overivew (2023f)_revised
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01_Verilog structural and dataflow modeling (2023f)
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02_Verilog behavioral level modeling (2023f)
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03_logic synthesis and design flow (2023f)
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05_pipelined THUMB CPU (2023f)
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HDL_HW1_adder
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HW1_modeling an adder in three Verilog levels_revised_4(2023f)
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HDL_HW2_pipelined add_sub_multiplier
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HW2_pipelined add_sub_multiplier in both RTL and gate-level_revised_3 (2023f)
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HDL_HW3_ pipelined THUMB CPU
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HW3_ pipelined THUMB CPU (2023f)
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99_1_midterm exam review
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HW4_color conversion and Sobel edge operation with line buffer (2023f)
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HDL_HW4_Sobel edge
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06_other Verilog modeling (2023f)
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04_Verilog Codes for Basic Components (2023f)
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2023f_hdl_midterm_new (with partial answers)_v7
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IEEE std 1364_1 (Verilog RTL synthesis)
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IEEE std 1364-2005 (Verilog HDL)
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07_Verilog 1995 vs 2001 (2023f)
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08_Verilog Codes for Advanced Components (2023f)
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HW5_first two VGG Conv layers (2023f)
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HDL_HW5_Accelerator for VGG-16
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09_VHDL_1_data type (2023f)
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HW6_memory generation for CNN accelerator
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HDL_HW6_Memory tor for CNN Accelerator
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HDL_HW6_Memory tor for CNN Accelerator
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12_Verilog versus VHDL (2023f)
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99_2_final exam review (2023f)
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11_VHDL_3_component, package, and configuration (2023f)
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10_VHDL_2_concurrent and sequential (2023f)
Co-Instructor(s)
蕭勝夫
蕭勝夫
Co-Instructor(s)
王韋竣
王韋竣
Co-Instructor(s)
郭昱
郭昱
Co-Instructor(s)
阮彥
阮彥
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