1131_硬體描述語言_CSE425
上課期間：從 即日起 到 無限期
課程介紹
課程安排
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00_outline and overivew (2024f)
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02_Verilog behavioral level modeling (2024f)
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IEEE std 1364-2005 (Verilog HDL)
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FXP_adder
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cover page of homework report
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testbench
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testbench explanationh
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HW1_modeling an adder in three Verilog levels (2024f)
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HDL_HW1_adder (2024f)
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01_Verilog structural and dataflow modeling (2024f)
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HDL_HW2_pipelined add_sub_multiplier (2024f)
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HW2_pipelined add_sub_multiplier (2024f)
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05_pipelined THUMB CPU (2024f)
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04_Verilog Codes for Basic Components (2024f)
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02_Verilog behavioral level modeling (2024f)
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03_logic synthesis and design flow (2024f)
教師 / 蕭勝夫
教師 / 郭昱
教師 / 黃宥翔
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