1131_HARDWARE DESCRIPTION LANGUAGES_CSE425
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
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00_outline and overivew (2024f)
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02_Verilog behavioral level modeling (2024f)
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IEEE std 1364-2005 (Verilog HDL)
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FXP_adder
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cover page of homework report
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testbench
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testbench explanationh
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HW1_modeling an adder in three Verilog levels (2024f)
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HDL_HW1_adder (2024f)
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01_Verilog structural and dataflow modeling (2024f)
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HDL_HW2_pipelined add_sub_multiplier (2024f)
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HW2_pipelined add_sub_multiplier (2024f)
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05_pipelined THUMB CPU (2024f)
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03_logic synthesis and design flow (2024f)
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04_Verilog Codes for Basic Components (2024f)
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02_Verilog behavioral level modeling (2024f)
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tb_thumb
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thumb_defs
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thumb
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thumb_syn
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HDL_HW3_pipelined_THUMB (2024f)
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HW3_ pipelined THUMB CPU (2024f)
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Appendix A (THUMB)
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99_1_hdl_midterm exam review
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07_Verilog 1995 vs 2001 (2024f)
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06_other Verilog modeling (2024f)
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HW4_color conversion and Sorbel edge operation with line buffer_revised (2024f)
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HDL_HW4_Sorbel edge_revised (2024f)
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HW4作業說明
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08_Verilog Codes for Advanced Components (2024f)
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09_VHDL_1_data type (2024f)
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12_Verilog versus VHDL (2024f)
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HDL_HW6_Memory tor for CNN Accelerator (2024f)
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HDL_HW5_Accelerator for VGG-16 (2024f)
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11_VHDL_3_component, package, and configuration (2024f)
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10_VHDL_2_concurrent and sequential (2024f)
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99_2_hdl_final exam review (2024f)
Co-Instructor(s)
蕭勝夫
蕭勝夫
Co-Instructor(s)
郭昱
郭昱
Co-Instructor(s)
黃宥翔
黃宥翔
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