1131_PRACTICAL DIGITAL SYSTEMS DESIGN_EE3705
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
-
00_Overview
-
01_Introduction
-
02-I_Basic Verilog Coding _Combinational Logic
-
02-II_Basic Verilog Coding _Combinational Logic
-
Homework Submission Rules and Demonstration
-
03-I_SOC Server Overview
-
HW1
-
04_Adder designs
-
HW2
-
20170426_Midterm Examination
-
05_Synopsys Design Compiler Logic Synthesis EDA Tool
-
06_Basic Verilog Coding &Sequential Logic
-
HW3
-
07_Multiplier designs
-
HW4
-
Final project IDC
-
08_RTL Coding Guildlines
Co-Instructor(s)
謝東佑
謝東佑
Co-Instructor(s)
鄞振祐
鄞振祐
Co-Instructor(s)
黃悅慈
黃悅慈
Co-Instructor(s)
張鈞詔
張鈞詔
Related Courses
|
|
||||||
|
|
|
||||||
|
|
|
||||||
|