1131_PRACTICAL DIGITAL SYSTEMS DESIGN_EE3705
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
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00_Overview
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01_Introduction
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02-I_Basic Verilog Coding _Combinational Logic
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02-II_Basic Verilog Coding _Combinational Logic
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Homework Submission Rules and Demonstration
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03-I_SOC Server Overview
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HW1
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04_Adder designs
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HW2
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20170426_Midterm Examination
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05_Synopsys Design Compiler Logic Synthesis EDA Tool
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06_Basic Verilog Coding &Sequential Logic
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HW3
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07_Multiplier designs
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HW4
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Final project IDC
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08_RTL Coding Guildlines
Co-Instructor(s)
謝東佑
謝東佑
Co-Instructor(s)
鄞振祐
鄞振祐
Co-Instructor(s)
黃悅慈
黃悅慈
Co-Instructor(s)
張鈞詔
張鈞詔
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