1122_PRACTICAL DIGITAL SYSTEMS DESIGN_EE3705
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
-
00_Overview
-
01_Introduction
-
02-I_Basic Verilog Coding &Combinational Logic
-
02-II_Basic Verilog Coding &Combinational Logic
-
03_SOC Overview
-
PDSD作業基本注意事項
-
HW1-1
-
04_Adder designs
-
HW1-2
-
20170426_Midterm Examination
-
05_Synopsys Design Compiler Logic Synthesis EDA Tool
-
HW2
-
06_Basic Verilog Coding &Sequential Logic
-
HW3
-
112-2_PDSD_Final Project
-
07_Multiplier designs
-
08_RTL Coding Guildlines
-
09_AI Accelerator Design for Intelligent Image Processing (I) - Fundamentals, Opportunities, and Challenges
-
10_AI Accelerator Design for Intelligent Image Processing (II) - Model Quantization
-
11_Workshop_Dynamic fixed-point quantization
-
12_AI Accelerator Design for Intelligent Image Processing (III) - Computational Sparsity
Co-Instructor(s)
謝東佑
謝東佑
Co-Instructor(s)
鄞振祐
鄞振祐
Co-Instructor(s)
鄭育玟
鄭育玟
Co-Instructor(s)
徐敬昕
徐敬昕
Related Courses
|
|
||||||
|
|
|
||||||
|
|
|
||||||
|
|
|
||||||
|