1131_SYSTEM-ON-CHIP TESTING_EE5729
Course Period：FromNow ~ Any Time
Course Intro
Course Plan
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00_Overview
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01_Introduction
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Homework Rule
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02_Fault model
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03_Faul simulation 1
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Homework1
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Midterm Examination_ref
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04_Test generation
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Homework2
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EX1_Fault simulation
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Homework3
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PODEM_worksheet
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PODEM_worksheet_after_class
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05_Testability Analysis
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06_Design for testability
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07_BIST
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07_Logic BIST_Intro1
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07_Logic BIST_LFSR
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07_Logic BIST_LFSR polynomial
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07_Logic BIST_Intro2
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07_Logic BIST_Parallel ORA MISR
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07_Logic BIST_Architecture
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07_Logic BIST_SerialORA
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[Ref-handout]07_BIST
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Seq_test_generation_worksheet
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Homework4
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SCOAP_worksheet
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test_operation_worksheet
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Homework5_v2
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Final Examination_ref
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EX2_ATPG_v2
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EX3_Scan-Insertion_ATPG_v2
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final_exam_classroom
Co-Instructor(s)
謝東佑
謝東佑
Co-Instructor(s)
甄致瑜
甄致瑜
Co-Instructor(s)
黃柏愷
黃柏愷
Co-Instructor(s)
廖國宏
廖國宏
Co-Instructor(s)
吳閏琮
吳閏琮
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